Title
DC performance and low frequency noise in n-MOSFETs using self-aligned poly-Si/SiGe Gate
Date Issued
24 December 2008
Access level
metadata only access
Resource Type
conference paper
Author(s)
Jiménez H.G.
Manera L.T.
Teixeira R.C.
Rautemberg M.F.
Diniz J.A.
Doi I.
Tatsch P.J.
Swart J.W.
Universidad Estatal de Campinas
Abstract
The characterization of an n-MOS transistor with poly- Si/SiGe Gate fabricated with the CMOS process entirely developed in the Center for Semiconductor Components (CCS) at UNICAMP is presented. The Gate layer was grown by vertical LPCVD at 800 °C. The resultant transistor has a channel region with oxide thickness of 30 nm and self-aligned thick S/D region. The DC and Gm characteristics of poly-Si/SiGe n-MOS transistor are reported. The turn-on in the I-V characteristics increases and at a drain-tosource bias Vds of +0.1 V nMOSFETs with 3 μm gate length had peak transconductance (μS) increased as well, compared with conventional n-MOS with poly-Si gate. The Gm characteristics and low frequency noise 1/f of the n-MOS transistors are studied using devices sizes with width of 20 μm and several lengths. Promising devices for RF and microwave circuit applications, show low 1/f and high values of transconductance. © The Electrochemical Society.
Start page
137
End page
146
Volume
14
Issue
1
Language
English
OCDE Knowledge area
Sistemas de automatización, Sistemas de control
Ingeniería eléctrica, Ingeniería electrónica
Scopus EID
2-s2.0-57749206779
Source
ECS Transactions
ISSN of the container
19385862
ISBN of the container
9781566776462
Conference
23rd Symposium on Microelectronics Technology and Devices, SBMicro2008
Sources of information:
Directorio de Producción Científica
Scopus