Title
Improving Speculative taskloop in Hardware Transactional Memory
Date Issued
01 January 2021
Access level
metadata only access
Resource Type
conference paper
Author(s)
Sao Paulo State University
Publisher(s)
Springer Science and Business Media Deutschland GmbH
Abstract
Previous work proposed and evaluated Speculative taskloop (STL) on Intel Core implementing new clauses and constructs in OpenMP. The results indicated that, despite achieving some speed-ups, there was a phenomenon called the Lost-Thread Effect that caused the performance degradation of STL parallelization. This issue is caused by the nonmonotonic scheduling implemented in the LLVM OpenMP Runtime Library. This paper presents an improvement in the STL mechanism by modifying the OpenMP runtime to allow monotonic scheduling of tasks generated by taskloop. We perform an evaluation with two different versions of the OpenMP runtime, both optimized for STL revealing that, for certain loops, infinite slowdowns (deadlocks) using the original OpenMP runtime can be transformed in speed-ups by applying monotonic scheduling. The experimental results show the performance improvement of STL using the modified version of the runtime, reaching speed-ups of up to 2.18 ×.
Start page
3
End page
17
Volume
12870 LNCS
Language
English
OCDE Knowledge area
Ingeniería de sistemas y comunicaciones Hardware, Arquitectura de computadoras
Scopus EID
2-s2.0-85115447282
ISSN of the container
03029743
ISBN of the container
978-303085261-0
Conference
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Sponsor(s)
This work is supported by FAPESP (grants 18/07446-8 and 18/15519-5).
Sources of information: Directorio de Producción Científica Scopus