Title
Software verification and validation within the (rational) unified process
Date Issued
01 January 2004
Access level
metadata only access
Resource Type
conference paper
Author(s)
Fuhrman C.
Djlive F.
PALZA VARGAS, EDGARDO LEMUEL
École de Technologie Supérieure
Publisher(s)
Institute of Electrical and Electronics Engineers Inc.
Abstract
We discuss the integration of software verification and validation activities (as defined by the IEEE Std. 1012) within the unified process. We compare and contrast these two process frameworks, and identify the aspects of verification and validation that are directly supported, partially supported or not supported by the unified process.
Start page
216
End page
220
Language
English
OCDE Knowledge area
Ingeniería de sistemas y comunicaciones Informática y Ciencias de la Información
DOI
10.1109/SEW.2003.1270746
Scopus EID
2-s2.0-16344395064
ISBN of the container
0769520642
Conference
Proceedings - 28th Annual NASA Goddard Software Engineering Workshop, SEW 2003
Sponsor(s)
Natural Sciences and Engineering Research Council of Canada
Sources of information: Directorio de Producción Científica Scopus