Title
Hardware managers with file system support for faster dynamic partial reconfiguration
Date Issued
14 October 2014
Access level
metadata only access
Resource Type
conference paper
Author(s)
Escobar F.A.
Chang X.
Valderrama C.
Universidade Federal Do Rio Grande Do sul
Publisher(s)
Institute of Electrical and Electronics Engineers Inc.
Abstract
FPGA-based platforms allow implementing reconfigurable systems that can change functionality of portions of hardware at runtime. For this purpose, non-volatile, off-chip storage is required to hold the partial-configuration bitstreams that will be used for reconfiguration. Accessing such devices requires a high CPU usage or a dedicated hardware such as a Direct Memory Access (DMA) module, especially when reading from mass storage units using file systems. Relieving the processor from bitstreams acquisition and reconfiguration control promotes parallelism and better task scheduling. This paper presents a dedicated Intellectual Property (IP) block which efficiently retrieves bitstreams from a FAT16 formatted memory and independently performs partial reconfiguration at the highest possible speed. Three versions of the same module are proposed to enable the creation of systems capable of accessing the memory with different protocols and control units. The evaluation results show the advantages of our approach in terms of reconfiguration and reading speed, reduced area overhead, flexibility and ease of use.
Start page
205
End page
210
Language
English
OCDE Knowledge area
Hardware, Arquitectura de computadoras
Scopus EID
2-s2.0-84911440033
ISBN of the container
978-147994293-0
Conference
Proceedings - 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2014 - 12th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2014
Sources of information: Directorio de Producción Científica Scopus