Title
A Dependency-Free Real-Time UHD Architecture for the Initial Stage of HEVC Motion Estimation
Date Issued
14 March 2019
Access level
metadata only access
Resource Type
conference paper
Author(s)
Publisher(s)
Institute of Electrical and Electronics Engineers Inc.
Abstract
Novel coding tools and algorithms were proposed in the High Efficiency Video Coding Standard (HEVC), and are still being proposed over the HM reference software in order to achieve a better compression efficiency, decrease encoding time, make its stages suitable for hardware implementation, and other independent improvements. Particularly, for the initial stage of the motion estimation (ME) process, the Advanced Motion Vector Prediction (AMVP) and the Dynamic Search Range (DSR) algorithms were introduced in the field targeting the determination of the motion vector predictor (MVP), also used as the search center, and search range (SR), which are parameters needed in the subsequent steps of motion estimation (ME). However, the significant complexity of these new tools enhances the need to develop hardware (HW) accelerators. Furthermore, in the field of HW architectures for video compression, techniques that solve dependency problems (which are detrimental to performance)-in this case, between sub-stages of ME-were proposed by some authors. Thereupon, an integrated and synchronized dependency-free HW architecture for the initial stage of the ME process-regarding MV prediction and SR calculation-is proposed in this paper. Synthesis results on a middle ground FPGA (Kintex-7 xc7k70tfbv676-1) show that the integrated architecture can achieve a throughput up to 8K at 72 frames-per-second (4:2:2 subsampling) while using a maximum of 7.04% of the FPGA resources (on slice LUT's).
Start page
157
End page
160
Language
English
OCDE Knowledge area
Ingeniería eléctrica, Ingeniería electrónica
Subjects
Scopus EID
2-s2.0-85064160262
Resource of which it is part
2019 IEEE 10th Latin American Symposium on Circuits and Systems, LASCAS 2019 - Proceedings
ISBN of the container
9781728104522
Conference
10th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2019Armenia24 February 2019through 27 February 2019
Sponsor(s)
This work presented an integrated and synchronized dependency-free HW architecture targeting the initial stage of HEVC ME, which includes the MVP determination and SR calculation. To do so, state-of-the-art algorithms that bring improvements over the HM reference software were implemented in HW, such as the DSR [8] and AMVP tools. Additionally, novel simplifications/improvements to the required computations —such as the utilization of the WSAD [11] as a distortion metric in AMVP and WSAD as an approximation to euclidean distance in DSR— were proposed. Moreover, HW dependency-problem solving features were used [12] and also proposed for the DSR module. Finally, the proposed architecture was optimized to achieve a real-time UHD processing capability (8K@72fps) using relatively low resources (a maximum of 7.04% on slice LUT’s) of a middle ground FPGA (Kintex-7 xc7k70tfbv676-1). ACKNOWLEDGMENTS To the members of the Microelectronics Research Group (GµE) and to the Pontifical Catholic University of Peru (PUCP) for supporting this work through the Thesis Program Award (PADET).
Sources of information:
Directorio de Producción Científica
Scopus