The use of reconfigurable devices, such as FPGAs, in nanosatellites allows the prototyping and evaluation in flight of different categories of designs of interest to the aerospace technology. It includes blending of experimental or well-proven legacy software executing on microprocessors with out-of-core accelerators and dedicated logic circuits, or even the conversion of such software to logic circuits using high-level synthesis (HLS). An additional feature discussed in this work, which is relevant to the scientific mission of the NanosatC-BR2 nanosatellite, is the use of SRAM-based FPGA as radiation particle sensor exploiting the susceptibility of SRAM memory to bit-flips caused by radiation. The process for bit-flip recording by bitstream readback is presented as well as a set of experimental designs implemented on the FPGA for data processing. As the status of these experimental designs must be reliably tracked by a supervisory circuit implemented on the same SRAM-based FPGA, errors caused by the bit-flips must be considered. Mitigation using triple modular redundancy (TMR) is analyzed using fault injection, suggesting that a fine grain distributed TMR approach can increase mission time of the supervisory module by 8x at a target reliability of 95%, but with a penalty of 40% in the estimated total power consumption of the FPGA. Conversely, a blockwise TMR approach can increase mission time of the supervisory module by 6x at the same target reliability with no increase in the estimated total power consumption.