This work presents the design and verification of the main block of a Gigabit Ethernet switch for an ASIC based on the NetFPGA platform [1]. The main function of the Layer-2 classification engine is to forward Ethernet frames to their corresponding output ports. To accomplish this task the block stores the source MAC address from frames in a SRAM memory and associates it to one of the input ports. This classification engine uses a hashing scheme that has been proven to be effective in terms of performance and implementation costs. It can lookup constantly 62.5 million frames per second, which is enough to work at wire-speed rate in a 42-port Gigabit switch. The main challenge was to achieve wire-speed rate during the learning process using external SRAM memory. This means that the bandwidth will not be reduced when new flows appear. This block was synthesized with an 180nm process and verified using System Verilog. A constrained random stimulus approach is used in a layered-testbench environment with self-checking capability. ©2010 IEEE.