Title
Implementation of a fixed-point 2D Gaussian Filter for Image Processing based on FPGA
Date Issued
23 December 2015
Access level
metadata only access
Resource Type
conference paper
Author(s)
Cabello F.
Iano Y.
Arthur R.
Universidad Estadual de Campinas
Publisher(s)
IEEE Computer Society
Abstract
One of the very useful techniques in Image Processing is the 2D Gaussian Filter, especially when smoothing images. However, the implementation of a 2D Gaussian Filter requires heavy computational resources, and when it comes down to real-time applications, efficiency in the implementation is vital. Floating-point math represents an obstacle for this, as its implementation requires a large amount of computational power in order to achieve real-time image processing. On the other hand, a fixed-point approach is much more suitable; implementation of a 2D Gaussian Filter in FPGA using fixed-point arithmetic provides efficiency in the processing and reduction in computational costs. The purpose of this study is to present the FPGA resource usage for different sizes of Gaussian Kernel; to provide a comparison between fixed-point and floating point implementations; and to define the amount of bits are necessary to use in order to have a Root Mean Square Error (RMSE) below 5%.
Start page
28
End page
33
Volume
2015-December
Language
English
OCDE Knowledge area
Ingeniería eléctrica, Ingeniería electrónica Ciencias de la computación
Scopus EID
2-s2.0-84962220498
Source
Signal Processing - Algorithms, Architectures, Arrangements, and Applications Conference Proceedings, SPA
Resource of which it is part
Signal Processing - Algorithms, Architectures, Arrangements, and Applications Conference Proceedings, SPA
ISSN of the container
23260262
ISBN of the container
978-836206523-3
Conference
19th IEEE Signal Processing Algorithms, Architectures, Arrangements, and Applications Conference, SPA 2015
Sources of information: Directorio de Producción Científica Scopus