Title
Separable FIR filtering in FPGA and GPU implementations: Energy, performance, and accuracy considerations
Date Issued
09 November 2011
Access level
metadata only access
Resource Type
journal article
Author(s)
Publisher(s)
Actas de congresos
Abstract
Digital video processing requires significant hardware resources to achieve acceptable performance. Digital video processing based on dynamic partial reconfiguration (DPR) allows the designers to control resources based on energy, performance, and accuracy considerations. In this paper, we present a dynamically reconfigurable implementation of a 2D FIR filter where the number of coefficients and coefficients values can be varied to control energy, performance, and precision requirements. We also present a high-performance GPU implementation to help understand the trade-offs between these two technologies. Results using a standard example of 2D Difference of Gaussians (DOG) filter indicate that the DPR implementation can deliver real-time performance with energy per frame consumption that is an order of magnitude less than the GPU. On the other hand, at significantly higher energy consumption levels, the GPU implementation can deliver very high performance. © 2011 IEEE.
Start page
363
End page
368
Language
English
OCDE Knowledge area
Ingeniería, Tecnología
Scopus EID
2-s2.0-80455127079
ISBN
9780769545295
Source
Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
Sponsor(s)
Términos controlados por ingeniería
Utilización de energía ; Conjuntos de puertas programables en campo (FPGA) ; filtros FIR ; Sistemas multimedia ; Procesamiento de señal de vídeo
Términos no controlados de ingeniería
Controlar la energía ; Diferencia de Gaussianos ; Procesamiento de vídeo digital ; filtrado FIR ; Implementación de GPU ; Recursos de hardware ; EN dinámica ; Reconfigurable ; Rendimiento en
Título principal de ingeniería
Gráficos de computadora
Sources of information:
Directorio de Producción Científica
Scopus