Title
Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices
Date Issued
26 July 1999
Access level
metadata only access
Resource Type
conference paper
Author(s)
Iparraguirre D.C.
Publisher(s)
Institute of Electrical and Electronics Engineers Inc.
Abstract
In this work an FIR filter is designed, combining the systolic architecture with the digit-serial technique. Multipliers are designed with this technique and the accumulator exploits these characteristics avoiding the lack of real-time computing capability and data processing speed. The system can be used in realtime digital signal and image processing applications. The simulation results presented were obtained using the FLEX 10K20 device of Altera.
Start page
147
End page
150
Language
English
OCDE Knowledge area
Ciencias de la computación
Ingeniería de sistemas y comunicaciones
Scopus EID
2-s2.0-34248657256
Resource of which it is part
Proceedings of the 3rd International Workshop on Design of Mixed-Mode Integrated Circuits and Applications
ISBN of the container
0780355881, 9780780355880
Conference
3rd International Workshop on Design of Mixed-Mode Integrated Circuits and Applications
Sources of information:
Directorio de Producción Científica
Scopus