Over the time, the development of the digital design field has increased dramatically and nowadays many different circuits and systems are designed for multiple purposes in short time lapses. However, this development has not been based only in the enhancement of the design tools, but also in the improvement of the verification tools. Which is a consequence of the outstanding role of the verification process that certifies the adequate performance and the fulfillment of the requirements. In the verification industry, methodologies such as UVM, OVM and VMM are used, but they have not been implemented yet in countries such as Peru and they seem inconvenient for educational purposes. This research defines an alternative methodology for the verification process of low and medium level designs contributing to the development of more complex and elaborated designs in countries with little or none verification background and limited verification tools. The methodology proposed is a functional verification methodology described in SystemVerilog and its effectiveness is evaluated in the verification of an AES encryption module taken from [3].