We recently presented an analysis of a Limited Intermediate Buffer (LIB) switch [1] consisting of input buffers and a limited amount of buffers in the switch fabric, where contention for the output ports occurs. A novel scheduling scheme based on head of line blocking was proposed, which improves the performance significantly. For uniform random traffic, a 16 x 16 LIB switch has an achievable throughput equal to 87.5%. In this paper, we examine the switch performance under two delay dependent priority classes and show that the achievable throughput can be increased to 91%. To build large size switching systems, a multistage interconnection network is used, which meets the demands of large scale ATM switch design, such as (1) modularity (2) relaxed synchronization (3) guaranteed high performance (i. e. high throughput, low variability of delay) without requiring internal speed-up and (4) maintaining packet sequence integrity. The simulation results of three-stage interconnection networks prove the efficacy of the LIB switch architecture and the proposed scheduling scheme.