SRAM-based FPGAs are attractive to critical applications due to their reconfiguration capability, which allows the design to be adapted on the field under different upset rate environments. High level Synthesis (HLS) is a powerful method to explore different design architectures in FPGAs. In this paper, we analyze four different design architectures implemented in a 28 nm SRAM-based FPGA under fault injection to analyze the probability of errors of them. We compare the information of essential bits provided by Xilinx with the susceptible bits obtained by fault injection. The dynamic cross section, soft error rate and mean work between failures are calculated based on the experimental results. There is a trade-off in the number of errors classified as silent data corruption and timeout errors according to the architecture and DSP blocks usage. The proposed characterization method can be used to guide designers to select the most efficient architecture concerning the susceptibility to upsets and performance efficiency.