DC performance and Low Frequency Noise in p-MOS transistor with poly-Si/SiGe Gate fabricated with the CMOS process entirely developed in the Center for Semiconductor Components at UNICAMP is presented. After deposition, films of poly-Si and poly SiGe were implanted by phosphorus ions. The transistor has a channel region with silicon oxide thickness of 30 nm and a poly-Si/SiGe gate region with self-aligned thick S/D region. The parameters on threshold, sub-threshold and low frequency noise (1/f) of poly-Si/SiGe p-MOS transistor are reported. The turn-on in the I-V characteristics increases and at a drain-to-source bias VDS of -0.1 V p-MOSFETs with L poly=1.57μm gate length had peak transconductance (Gm) increased as well, compared with conventional p-MOS with poly-Si gate. The DC and 1/f characteristics of the p-MOS transistors are studied using several devices sizes. Devices show low 1/f and high values for Gm parameters and make them promising devices for RF and microwave circuit applications. © The Electrochemical Society.