The Jicamarca Radio Observatory (JRO), funded by the USA National Science Foundation (NSF), operates several radars for different applications, from the main radar, an incoherent scatter radar used mainly for ionospheric activity observations, to ionosondes and wind profilers. Most of these radars use a centralized modular control system that commands all the radar sequences that require the radar modules, these tasks and sequences are controlled by pulsed digital signals. The device responsible for this operation is called the Radar Controller. A large number of customized Radar Controller versions were developed and built at JRO for decades, since the utilization of its first acquisition system. The current version of the Radar Controller is based on an RTL design written on VHDL language that implements a custom arbitrary waveform generator connected to an SRAM memory that stores all the data a given waveform needs. The Radar Controller uses a register based architecture to communicate between blocks internally. In JRO we use a Spartan 6 FPGA and it is controlled by a Tiva C microcontroller board which has an Ethernet port. A Restful API has been implemented on the microcontroller for user configuration. This paper will cover the VHDL RTL design of the current version of the Radar Controller core.