In this paper, a digit-serial decimating filter using a systolic architecture is presented for digit-sizes 1, 2 and 4. The flip-flop's clock enable inputs are used for the multipliers to work at half the clock frequency, so it is possible for the filter to work at a higher frequency than the apparent result of the Timing simulation. The CPLD features are used to increase the clock frequency, as well as the different synthesis options. This design has a real-time computing capability. The architecture has been designed with Max+Plus II 9.01 and simulated using FLEX 10K devices of the Altera family.