This paper details how the VHDL-AMS language can be used to support steps I through IV of a six step SoC (system on chip) design and synthesis methodology with high productivity gains. This is because about 80 to 90% of the VHDL code used for synthesis in phases V and VI is the same code developed in phases I through IV with the VHDL-AMS language. A case study involving the motor drive of a hybrid electric vehicle is used to demonstrate the details of the methodology. The SoC is a Spartan 3A FPGA of Xilinx. Detailed models, simulations, VHDL-AMS code and VHDL synthesis code is included. ©2008 IEEE.